Counter.vhdl

Summary

Lines:

7 of 8 covered (87.5%)

Branches:

6 of 8 taken (75.0%), 2 lines partially

Coverage:

81.2%

Directory:

src

Missed lines:

27

Source

src/Counter.vhdlcoveredpartialuncoveredexcludednot executable
1library ieee;
2use     ieee.std_logic_1164.all;
3use     ieee.numeric_std.all;
4
5
6entity Counter is
7	generic (
8		BITS : positive := 8
9	);
10	port (
11		Clock  : in  std_logic;
12		Reset  : in  std_logic;
13		Enable : in  std_logic;
14		Value  : out unsigned(BITS - 1 downto 0);
15		Wrap   : out std_logic
16	);
17end entity;
18
19
20architecture rtl of Counter is
21	signal Count : unsigned(BITS - 1 downto 0) := (others => '0');
22begin
231	process(Clock)
24	begin
252048		if rising_edge(Clock) then
261024			if Reset = '1' then
270				Count <= (others => '0');
281024			elsif Enable = '1' then
29700				Count <= Count + 1;
30			end if;
31		end if;
32	end process;
33
34701	Value <= Count;
35701	Wrap  <= '1' when Count = (Count'range => '1') else '0';
36end architecture;